LUT Based Generalized Parallel Counters for State-of-art FPGAs

Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases

Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations

Modern day field programmable gate arrays (FPGAs) have very huge and versatile logic resources resulting in the migration of their application domain from prototype designing to low and medium volume production designing. Unfortunately most of the work pertaining to FPGA implementations does not focus on the technology dependent optimizations that can implement a desired functionality with reduced cost. In this paper we consider the mapping of simple ripple carry fixed-point adders (RCA) on look-up table (LUT) based FPGAs. The objective is to transform the given RCA Boolean network into an optimized circuit netlist that can implement the desired functionality with minimum cost. We particularly focus on 6-input LUTs that are inherent in all the modern day FPGAs. Technology dependent optimizations are carried out to utilize this FPGA primitive efficiently and the result is compared against various adder designs. The implementation targets the XC5VLX30-3FF324 device from Xilinx Virtex-5 FPGA family. The cost of the circuit is expressed in terms of the resources utilized, critical path delay and the amount of on-chip power dissipated. Our implementation results show a reduction in resources usage by at least 50%; increase in speed by at least 10% and reduction in dynamic power dissipation by at least 30%. All this is achieved without any technology independent (architectural) modification

Global investments in pandemic preparedness and COVID-19: development assistance and domestic spending on health between 1990 and 2026

Background The COVID-19 pandemic highlighted gaps in health surveillance systems, disease prevention, and treatment globally. Among the many factors that might have led to these gaps is the issue of the financing of national health systems, especially in low-income and middle-income countries (LMICs), as well as a robust global system for pandemic preparedness. We aimed to provide a comparative assessment of global health spending at the onset of the pandemic; characterise the amount of development assistance for pandemic preparedness and response disbursed in the first 2 years of the COVID-19 pandemic; and examine expectations for future health spending and put into context the expected need for investment in pandemic preparedness. Methods In this analysis of global health spending between 1990 and 2021, and prediction from 2021 to 2026, we estimated four sources of health spending: development assistance for health (DAH), government spending, out-of-pocket spending, and prepaid private spending across 204 countries and territories. We used the Organisation for Economic Co-operation and Development (OECD)'s Creditor Reporting System (CRS) and the WHO Global Health Expenditure Database (GHED) to estimate spending. We estimated development assistance for general health, COVID-19 response, and pandemic preparedness and response using a keyword search. Health spending estimates were combined with estimates of resources needed for pandemic prevention and preparedness to analyse future health spending patterns, relative to need. Findings In 2019, at the onset of the COVID-19 pandemic, US$9·2 trillion (95$7·3 trillion (95% UI 7·2–7·4) in 2019; 293·7 times the $24·8 billion (95$43·1 billion in development assistance was provided to maintain or improve health. The pandemic led to an unprecedented increase in development assistance targeted towards health; in 2020 and 2021, $1·8 billion in DAH contributions was provided towards pandemic preparedness in LMICs, and$37·8 billion was provided for the health-related COVID-19 response. Although the support for pandemic preparedness is 12·2% of the recommended target by the High-Level Independent Panel (HLIP), the support provided for the health-related COVID-19 response is 252·2% of the recommended target. Additionally, projected spending estimates suggest that between 2022 and 2026, governments in 17 (95% UI 11–21) of the 137 LMICs will observe an increase in national government health spending equivalent to an addition of 1% of GDP, as recommended by the HLIP. Interpretation There was an unprecedented scale-up in DAH in 2020 and 2021. We have a unique opportunity at this time to sustain funding for crucial global health functions, including pandemic preparedness. However, historical patterns of underfunding of pandemic preparedness suggest that deliberate effort must be made to ensure funding is maintained

Technology - Dependent Optimization of FIR Filters based on Carry - Save Multiplier and 4:2 Compressor unit

This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this pa per are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filte rs and restructure these units to achieve improved integration levels. The technology optimized Boolean networks are then coded using instantiation based coding strategies. The Xilinx tool then uses its own optimization strategies to further optimize the networks and generate circuits with high logic densities and reduced depths. Experimental results indicate a significant improvement in performance over traditional realizations. An important property of technology-dependent optimizations is the simultaneous improvement in all the performance parameters. This is in contrast to the technology-independent optimizations where there is always an application driven trade-off between different performance parameters

Achieving Performance Speed-up in FPGA Based Bit-Parallel Multipliers using Embedded Primitive and Macro support

Modern Field Programmable Gate Arrays (FPGA) are fast moving into the consumer market and their domain has expanded from prototype designing to low and medium volume productions. FPGAs are proving to be an attractive replacement for Application Specific Integrated Circuits (ASIC) primarily because of the low Non-recurring Engineering (NRE) costs associated with FPGA platforms. This has prompted FPGA vendors to improve the capacity and flexibility of the underlying primitive fabric and include specialized macro support and intellectual property (IP) cores in their offerings. However, most of the work related to FPGA implementations does not take full advantage of these offerings. This is primarily because designers rely mainly on the technology-independent optimization to enhance the performance of the system and completely neglect the speed-up that is achievable using these embedded primitives and macro support. In this paper, we consider the technology-dependent optimization of fixed-point bit-parallel multipliers by carrying out their implementations using embedded primitives and macro support that are inherent in modern day FPGAs. Our implementation targets three different FPGA families viz. Spartan-6, Virtex-4 and Virtex-5. The implementation results indicate that a considerable speed up in performance is achievable using these embedded FPGA resources

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources